1. Field of the Invention
The present invention relates generally to methods for forming dual damascene structures within microelectronic fabrications. More particularly, the present invention relates to methods for forming low dielectric constant dual damascene structures within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Such comparatively low dielectric constant dielectric materials generally have dielectric constants in a range of from about 3.5 to less than about 2.0. For comparison purposes, microelectronic dielectric layers formed within microelectronic fabrications from conventional silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically have comparatively high dielectric constants in a range of from greater than about 4.0 to about 8.0. Similarly, such patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are typically formed within microelectronic fabrications while employing damascene methods, including in particular dual damascene methods.
Microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are desirable in the art of microelectronic fabrication formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as such microelectronic dielectric layers provide microelectronic fabrications which may theoretically operate at higher microelectronic fabrication speeds, with attenuated patterned microelectronic conductor layer parasitic capacitance and attenuated patterned microelectronic conductor layer cross-talk.
Similarly, damascene methods are desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials insofar as damascene methods are comparatively simple fabrication methods which may often be employed to fabricate microelectronic structures which are not otherwise practicably accessible in the art of microelectronic fabrication.
While damascene methods are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. In that regard, while damascene methods are generally successful for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, damascene methods do not always uniformly provide such patterned microelectronic conductor layers within optimally low dielectric constant dielectric material layer constructions.
It is thus desirable in the art of microelectronic fabrication to provide damascene methods which may be employed in the art of microelectronic fabrication for uniformly providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively and optimally low dielectric constant dielectric material layer constructions.
It is towards the foregoing object that the present invention is directed.
Various damascene methods have been disclosed in the art of microelectronic fabrication for forming within microelectronic fabrications damascene structures with desirable properties.
Included among the damascene methods, but not limited among the damascene methods, are damascene methods disclosed within: (1) Yu et al., in U.S. Pat. No. 6,004,883 (a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via formed through a dielectric layer within a microelectronic fabrication absent use of an extrinsic etch stop layer when forming the corresponding trench contiguous with the corresponding via, by employing when forming the dielectric layer a bilayer dielectric layer comprising: (1) a first dielectric material layer which is not susceptible to etching within an oxygen containing plasma, having formed thereupon; (2) a second dielectric material layer which is susceptible to etching within the oxygen containing plasma); and (2) Lin et al., in U.S. Pat. No. 6,042,999 (a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer within a microelectronic fabrication while avoiding substrate damage when forming the corresponding trench contiguous with the corresponding via, by employing a sacrificial material layer formed into the via when forming contiguous therewith the trench).
Desirable in the art of microelectronic fabrication are additional damascene methods which may be employed in the art of microelectronic fabrication for uniformly providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively and optimally low dielectric constant dielectric material layer constructions.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material.
A second object of the present invention is to provide a damascene method in accord with the first object of the present invention, wherein the patterned microelectronic conductor layer is uniformly formed within an optimally low dielectric constant dielectric material layer construction.
A third object of the present invention is to provide a damascene method in accord with the first object of the present invention and the second object of the present invention, wherein the damascene method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a dual damascene aperture within a dielectric layer. To practice the method of the present invention, there is first provided a substrate having an active product region adjacent a non active product region. There is then formed over the substrate a first dielectric layer in turn having formed thereover a second dielectric layer. There is also formed over the substrate and interposed between the first dielectric layer and the second dielectric layer an etch stop layer in the non active product region, but not in the active product region. There is then formed through the second dielectric layer and the first dielectric layer in the active product region a dual damascene aperture comprising a trench contiguous with a via. Within the present invention, when forming the trench within the dual damascene aperture there is employed an etch method which forms a dummy trench within the non active product region. The dummy trench reaches the etch stop layer and the etch method senses the etch stop layer for end point detection when forming the trench within the dual damascene aperture within the active product region.
Within the present invention, a contiguous patterned conductor interconnect and patterned conductor stud layer may be formed into the dual damascene aperture, which comprises the trench contiguous with the via which in turn generally reaches a contact region, while employing a blanket conductor layer deposition and planarizing method, preferably a blanket conductor layer deposition and chemical mechanical polish (CMP) planarizing method.
The present invention provides a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material, wherein the patterned microelectronic conductor layer is uniformly formed within an optimally low dielectric constant dielectric material layer construction.
The present invention realizes the foregoing object by providing in a first instance a substrate having an active product region adjacent a non active product region. Within the present invention, the substrate has formed thereover a first dielectric layer in turn having formed thereover a second dielectric layer, wherein there is also formed interposed between the first dielectric layer and the second dielectric layer an etch stop layer in the non active product region, but not in the active product region. Thus, when there is formed through the second dielectric layer and the first dielectric layer in the active product region a dual damascene aperture comprising a trench contiguous with a via, there may be employed an etch method which forms a dummy trench within the non active product region, such that: (1) the dummy trench reaches the etch stop layer; and (2) the etch method senses the etch stop layer, for end point detection when forming the trench within the dual damascene aperture within the active product region. Since within the present invention there is not employed within the active product region an etch stop layer, a microelectronic fabrication fabricated in accord with the present invention may be fabricated with an optimally low dielectric constant dielectric material layer construction within an active product region. Similarly, since when forming the trench within the active product region there is employed a dummy trench which reaches the etch stop layer and provides for sensation of the etch stop layer within the non active product region, a patterned conductor layer formed within the dual damascene aperture is formed with enhanced uniformity insofar as there may be avoided an otherwise non-uniform timed etch for forming the trench within the dual damascene aperture within the active product region.
The damascene method in accord with the present invention is readily commercially implemented.
As will be illustrated in greater detail within the context of the Description of the Preferred Embodiments, as set forth below, the damascene method of the present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed within the context of specific process limitations and specific materials limitations to provide the damascene method of the present invention. Since it is thus at least in part a series of specific process limitations and specific materials limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the damascene method of the present invention is readily commercially implemented.